Huawei’s He Tingbo Releases V2 of “Teresa’s Law” Paper – Engineering Breakthroughs in Post-Moore Chip Scaling

• Scope of Document: V1 focused on theoretical foundations; V2 provides engineering implementation and product roadmaps.
• Data Source: V1 was primarily conceptual; V2 utilizes empirical data from mass production.
• Scaling Focus: V1 established the time constant τ; V2 refines τ towards specific product evolution stages.
• Optimization Level: V1 suggested multi-level scaling; V2 introduces specific ‘cell-level continuous optimization’ via LogicFolding.

The semiconductor industry just got a major update on how chips will scale beyond Moore’s Law.

He Tingbo (何庭波), the head of Huawei (华为) semiconductor operations, dropped Version 2 of the “Time-Scaling Theory for Multi-level Electronic Systems” on July 3, 2026 on ChinaXiv (中国科学院科技论文预发布平台), the open-access repository for the Chinese Academy of Sciences.

The industry knows this framework as “Teresa’s Law” (韬定律).

And this isn’t just a minor patch.

This V2 release adds substantial engineering implementation details, measured quantitative data, and product evolution roadmaps that fundamentally reshape how we think about semiconductor advancement in the post-Moore era.

From Theory to Practice: What’s New in V2

The original V1 paper dropped back on May 25, establishing the theoretical foundation.

V2 takes a completely different approach.

Instead of staying in the realm of pure theory, this update grounds everything in real engineering data and actual product specs.

Here’s what makes this significant:

• Engineering implementation details that move beyond concept
• Quantitative data from actual mass production
• Clear product evolution roadmaps showing future trajectories
• Refined scaling theory centered around the time constant τ

For investors and technologists tracking chip innovation, this is a big deal.

Huawei (华为) isn’t just theorizing—they’re publishing concrete data showing how their approach actually works in silicon.

The 3D Logic Revolution: Breaking Through Traditional Stacking Limits

Here’s where things get really interesting from an engineering perspective.

The V2 paper dives deep into what Huawei (华为) calls the “gear ratio” concept within their core LogicFolding technology.

Traditional 3D chip stacking has always had a fundamental limitation: you can only layer functional blocks on top of each other.

It’s like stacking LEGO bricks—each layer has to be a complete, self-contained unit.

But as hybrid bonding pitches get smaller and approach the dimensions of top-layer metal wiring, everything changes.

The design space shifts from what the paper calls “macro-block level discrete optimization” to something much more powerful: “cell-level continuous optimization.”

What does this actually mean?

• You can now optimize the vertical partitioning of logic gates at the individual cell level
• This allows for globally optimal arrangements across the entire 3D structure
• Traditional approaches were stuck making local optimizations within functional blocks
• The new approach finds the absolute best placement for every single cell, regardless of traditional block boundaries

This isn’t a marginal improvement—this is a fundamental architectural shift in how semiconductor designers approach 3D chip design.

It’s the difference between optimizing individual rooms in a building versus optimizing the entire structure as one integrated system.

Real Data: The Kirin 2026 vs. Kirin 9030 Pro Comparison

Here’s what separates V2 from academic hand-waving: actual numbers.

The paper includes empirical data from mass production comparing the Kirin 2026 (麒麟2026) against the benchmark Kirin 9030 Pro (麒麟9030 Pro).

This is important because it puts theory into context.

The V2 release provides parameters across multiple dimensions:

• Voltage specifications
• Frequency capabilities
• Normalized power consumption metrics
• Die area measurements
• Power density calculations

Having these specs side-by-side isn’t just academic curiosity.

It validates whether Huawei’s (华为) theoretical framework actually delivers the improvements they’re claiming.

For product teams, supply chain partners, and investors, this data is the proof point everyone’s been waiting for.

Why This Matters for the Semiconductor Industry

The semiconductor world is hitting a wall.

Moore’s Law—the observation that transistor counts double roughly every two years—is running out of steam.

We’re hitting physical limits at the atomic scale.

So the industry is pivoting to alternative approaches like 3D chip stacking, chiplets, and heterogeneous integration.

Teresa’s Law (韬定律) represents one of the most ambitious frameworks for thinking about scaling in this post-Moore era.

Rather than making chips smaller, the approach focuses on making them smarter—optimizing how you arrange logic in three dimensions.

The V2 release validates this approach with real production data.

That’s significant validation.

The Investment Story Behind This

HiSilicon (海思), Huawei’s (华为) semiconductor design subsidiary, is investing heavily in this R&D trajectory.

We’re talking about ¥10,000,000,000 RMB ($1,377,000,000 USD) annually flowing into next-generation architecture research.

That’s not some startup’s monthly burn rate—that’s serious, sustained capital deployment.

While specific chip valuations vary by contract, this level of investment signals that Huawei (华为) isn’t just playing around with academic theory.

They’re building a competitive moat through semiconductor innovation.

For investors tracking Chinese tech, this is worth monitoring because it suggests Huawei (华为) is making progress on overcoming one of the biggest technical challenges in chip design: how to continue scaling performance when traditional lithography approaches have hit their limits.

What Comes Next?

The V2 paper release is really a midpoint check-in, not an endpoint.

By publishing on ChinaXiv (中国科学院科技论文预发布平台), an open-access platform, Huawei (华为) is getting the academic community’s feedback while also staking a claim on this innovation territory.

The Kirin 2026 (麒麟2026) specs suggest this approach is moving from theory into actual products.

That means within a few product cycles, we should see this technology show up in actual Huawei (华为) devices, not just research papers.

For founders building in the semiconductor space, for investors with exposure to chip design, and for technologists tracking the evolution of post-Moore scaling, Teresa’s Law (韬定律) is worth understanding.

The V2 release with empirical data just made it impossible to ignore.

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References

• Huawei’s He Tingbo Releases V2 of ‘Tao’s Law’ Paper – Cailian Press
• Time-Scaling Theory for Multi-level Electronic Systems V2 – ChinaXiv
• Latest Innovation Research – Huawei Official
• Advanced Semiconductor Roadmaps – HiSilicon